The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

May. 01, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mor M. Cohen, Haifa, IL;

Yaniv Hadar, Yokneam Elite, IL;

Ehud U. Shoor, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03M 1/10 (2006.01); H04L 25/03 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03949 (2013.01); H04L 7/00 (2013.01); H04L 7/033 (2013.01); H04L 25/03057 (2013.01); H04L 2201/02 (2013.01); H04L 2201/04 (2013.01);
Abstract

An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.


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