The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Jan. 04, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Jing Lin, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 21/308 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02129 (2013.01); H01L 21/02271 (2013.01); H01L 21/02532 (2013.01); H01L 21/308 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/1079 (2013.01); H01L 29/41791 (2013.01); H01L 29/66636 (2013.01);
Abstract

A fabrication method includes providing a base having a first transistor region and a second transistor region; forming a first stress layer in the first transistor region and a second stress layer in the second transistor region; forming a first covering layer on a surface of the first stress layer and a second covering layer on a surface of the second stress layer, with a gap between the first and the second covering layers exposing the surface of the base, and the neighboring side walls of the first and second covering layers have vertices pointing to each other; forming an isolation layer filling up the gap, and the isolation layer is higher than the vertices, exposing top surfaces of the first and second covering layers; and forming a third covering layer on the first covering layer and a fourth covering layer on the second covering layer.


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