The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Aug. 10, 2012
Applicants:

Marco A. Zuniga, Palo Alto, CA (US);

Yang LU, Fremont, CA (US);

Badredin Fatemizadeh, Sunnyvale, CA (US);

Jayasimha Prasad, San Jose, CA (US);

Amit Paul, Sunnyvale, CA (US);

Jun Ruan, Santa Clara, CA (US);

Inventors:

Marco A. Zuniga, Palo Alto, CA (US);

Yang Lu, Fremont, CA (US);

Badredin Fatemizadeh, Sunnyvale, CA (US);

Jayasimha Prasad, San Jose, CA (US);

Amit Paul, Sunnyvale, CA (US);

Jun Ruan, Santa Clara, CA (US);

Assignee:

Volterra Semiconductor LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66704 (2013.01); H01L 21/265 (2013.01); H01L 21/28105 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/063 (2013.01); H01L 29/0626 (2013.01); H01L 29/66696 (2013.01); H01L 29/78 (2013.01); H01L 29/7802 (2013.01); H01L 29/7825 (2013.01); H01L 29/7827 (2013.01); H01L 29/7835 (2013.01); H01L 29/0878 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/42368 (2013.01); H01L 29/456 (2013.01); H01L 29/4933 (2013.01);
Abstract

The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.


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