The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Aug. 31, 2017
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventors:

Yasuyuki Hoshi, Matsumoto, JP;

Yuichi Harada, Matsumoto, JP;

Takashi Shiigi, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 23/48 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/04 (2006.01); H01L 29/10 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/0465 (2013.01); H01L 21/0485 (2013.01); H01L 23/48 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/41741 (2013.01); H01L 29/51 (2013.01); H01L 29/66068 (2013.01); H01L 29/78 (2013.01); H01L 29/7802 (2013.01); H01L 29/417 (2013.01); H01L 29/7395 (2013.01);
Abstract

A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.


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