The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Jan. 31, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajiv Kapoor, University Place, WA (US);

Ronen Zohar, Sunnyvale, CA (US);

Mark Buxton, Chandler, AZ (US);

Zeev Sperber, Zichron Yaakov, IL;

Koby Gottlieb, Kiryat Tivon, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/02 (2006.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30021 (2013.01); G06F 7/026 (2013.01); G06F 9/3001 (2013.01); G06F 9/3016 (2013.01); G06F 9/30029 (2013.01); G06F 9/30036 (2013.01); G06F 9/30058 (2013.01); G06F 9/30094 (2013.01); G06F 9/30098 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3887 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01);
Abstract

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.


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