Full-duplex self-interference cancellation

Abstract

This disclosure describes methods and devices related to self-interference cancellation. A device is disclosed comprising: at least one memory storing computer-executable instructions; and at least one processor configured to access the at least one memory, wherein the at least one processor may be configured to execute the computer-executable instructions to cause to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain. The processor may be configured to execute the computer-executable instructions to determine at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain. The processor may be configured to execute the computer-executable instructions to determine a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain. The processor may be configured to execute the computer-executable instructions to determine a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain. The processor may be configured to execute the computer-executable instructions to determine a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain. The processor may be configured to execute the computer-executable instructions to determine a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response. The processor may be configured to execute the computer-executable instructions to determine an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.