The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2018
Filed:
Feb. 13, 2018
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Ching-Wen Hung, Tainan, TW;
Jia-Rong Wu, Kaohsiung, TW;
Yi-Hui Lee, Taipei, TW;
Ying-Cheng Liu, Tainan, TW;
Chih-Sen Huang, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 21/823871 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 27/092 (2013.01); H01L 29/66545 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01);
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.