Memory apparatus with non-volatile two-terminal memory and expanded, high-speed bus

Abstract

Providing for an electronic memory apparatus having high-density, non-volatile memory arrays in conjunction with a high-speed communication interface is disclosed herein. In some embodiments, the electronic memory apparatus can include multiple banks of two-terminal memory, communicatively connected to a modified dynamic random access memory bus and configured to operate according to a modified communication protocol. In one or more embodiments, the high-speed communication interface can comprise more than ten command and address pins to identify individual memory banks (or subsets of memory banks) of the multiple banks of memory, to facilitate bank-specific addressing for memory array operations. In some embodiments, the electronic memory can facilitate status information for subsets of memory banks to facilitate informed array operations, increasing duty cycle of the memory device.