The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Apr. 07, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Chang Yong Kang, Chandler, AZ (US);

Pierre Laurent, Kilnacrandy, IE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/60 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 21/64 (2013.01);
U.S. Cl.
CPC ...
G06F 21/602 (2013.01); G06F 9/30007 (2013.01); G06F 9/30101 (2013.01); G06F 9/3867 (2013.01); G06F 21/64 (2013.01);
Abstract

A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.


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