The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2018
Filed:
Sep. 24, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/08 (2016.01); G06F 12/0842 (2016.01); G06F 12/0855 (2016.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/0888 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/30047 (2013.01); G06F 9/383 (2013.01); G06F 12/08 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0855 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/0888 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/502 (2013.01);
Abstract
An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on the determination. For example, one embodiment of a processor comprises: a hierarchy of cache levels for caching data including at least a level 1 (L1) cache; cache occupancy determination logic to determine whether data associated with one or more subsequent operations is stored in one of the cache levels; and scheduling logic to schedule execution of the subsequent operations based on the determination of whether data associated with the subsequent operations is stored in the cache levels.