The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Dec. 24, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mahesh Wagh, Portland, OR (US);

Robert E. Gough, Cornelius, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 13/42 (2006.01); G06F 9/44 (2006.01); H04L 12/933 (2013.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/325 (2013.01); G06F 1/3206 (2013.01); G06F 1/3246 (2013.01); G06F 9/4418 (2013.01); G06F 13/42 (2013.01); H04L 49/15 (2013.01); Y02D 10/151 (2018.01); Y02D 50/20 (2018.01);
Abstract

A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.


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