The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Mar. 07, 2016
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/823437 (2013.01); H01L 21/823842 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/785 (2013.01); H01L 21/823431 (2013.01);
Abstract
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.