The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Jun. 30, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Stephen Alan Fanelli, San Marcos, CA (US);
Richard Hammond, Stoke-on-Trent, GB;
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/3063 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/265 (2013.01); H01L 21/3063 (2013.01); H01L 21/76256 (2013.01);
Abstract
A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.
Fanelli, Stephen. (2018). Porous silicon post processing (U.S. Patent No. 10134837). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10134837
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile