The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Aug. 21, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Han Chen, Tainan, TW;

Wei-Chi Chen, New Taipei, TW;

Ching Chang, New Taipei, TW;

Ming-Shing Chen, Kaohsiung, TW;

Chao-Hsien Wu, Hsinchu, TW;

Chia-Hui Hwang, Tainan, TW;

Lu-Ran Huang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/404 (2006.01); H01L 27/11 (2006.01); H01L 27/12 (2006.01); G11C 11/4097 (2006.01); G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11 (2013.01); G11C 11/404 (2013.01); G11C 11/4097 (2013.01); G11C 11/417 (2013.01); H01L 27/1211 (2013.01);
Abstract

A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.


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