Embedded pmos-trigger silicon controlled rectifier (scr) with suppression rings for electro-static-discharge (esd) protection

Abstract

An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.