The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Apr. 24, 2017
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Sun-kyoung Seo, Suwon-si, KR;
Seung-kwan Ryu, Seongnam-si, KR;
Cha-jea Jo, Yongin-si, KR;
Tae-Je Cho, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.