The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Apr. 08, 2015
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Thomas J. Hartswick, Underhill, VT (US);
Anthony K. Stamper, Williston, VT (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8222 (2006.01); H01L 23/522 (2006.01); H01L 21/288 (2006.01); H01L 23/64 (2006.01); H01L 21/768 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/2885 (2013.01); H01L 21/76885 (2013.01); H01L 23/585 (2013.01); H01L 23/645 (2013.01);
Abstract
An aspect of the invention includes a method for plating wires on a wafer comprising: forming an array of integrated circuit (IC) chips having a redistribution level; forming a kerf bus, the kerf bus separating each of the IC chips from each other, the kerf bus being connected to an edge of the wafer; forming an array of wires in the redistribution level of each IC chip; electrically connecting at least one wire in the array of wires on each IC chip to the kerf bus; and electroplating the array of IC chips.