The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Feb. 19, 2016
Applicant:
Silicon Storage Technology, Inc., San Jose, CA (US);
Inventors:
Hieu Van Tran, San Jose, CA (US);
Anh Ly, San Jose, CA (US);
Thuan Vu, San Jose, CA (US);
Hung Quoc Nguyen, Fremont, CA (US);
Assignee:
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/14 (2006.01); G11C 16/12 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/04 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01);
Abstract
Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.