The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Dec. 27, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ramadass Nagarajan, Portland, OR (US);

Jose S. Niell, Franklin, MA (US);

Michael T. Klinglesmith, Portland, OR (US);

Derek T. Bachand, Portland, OR (US);

Ganesh Kumar, Fort Collins, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 13/287 (2013.01); G06F 13/4282 (2013.01); G06F 2212/621 (2013.01);
Abstract

In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.


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