The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2018

Filed:

Nov. 15, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pavel I. Kryukov, Moscow, RU;

Stanislav Shwartsman, Haifa, IL;

Joseph Nuzman, Haifa, IL;

Alexandr Titov, Severodvinsk, RU;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/0837 (2016.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 12/0891 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0808 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0837 (2013.01); G06F 12/0842 (2013.01); G06F 12/0891 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/6042 (2013.01);
Abstract

An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.


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