The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Mar. 31, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Andrea Camuffo, Munich, DE;

Sandro Pinarello, Munich, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 27/08 (2006.01); H04W 52/02 (2009.01); H04L 12/26 (2006.01); H04W 72/04 (2009.01); H04J 11/00 (2006.01);
U.S. Cl.
CPC ...
H04W 52/02 (2013.01); H04L 27/08 (2013.01); H04L 43/16 (2013.01); H04J 11/00 (2013.01); H04W 72/0446 (2013.01); H04W 72/0473 (2013.01);
Abstract

An apparatus of a transmitter and method are provided, the apparatus comprising a processor that calculates a supply voltage (SV) value (SVV) to provide as an SV for a power amplifier (PA) of the transmitter for transmissions during a transmission time slot (TS). When the SV < an envelope tracking (ET) threshold (ETT), then the processor configures the PA to transmit a signal in an average power tracking (APT) mode that maintains the SV at the SVV during the TS. When the SV≥ETT, and an APT condition is met, then the processor configures the PA to transmit the signal in the APT mode. When the SV≥ETT, and the APT condition is not met, then the processor transmits by an adjustment to the SVV to track an amplitude modulation envelope during the TS in an ET mode.


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