The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Jul. 19, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Shenggao Li, Pleasanton, CA (US);
Stefan Rusu, Sunnyvale, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/091 (2006.01); H01L 23/48 (2006.01); G06F 13/40 (2006.01); H04L 7/00 (2006.01); H03L 7/07 (2006.01); H03L 7/081 (2006.01); G06F 1/12 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G06F 1/12 (2013.01); G06F 13/4027 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H03L 7/07 (2013.01); H03L 7/0814 (2013.01); H03L 7/091 (2013.01); H04L 7/0012 (2013.01); H04L 7/0025 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/06541 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract
Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.