The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Nov. 18, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Ni-Wan Fan, Tao-yuan, TW;

Sheng-Hsiung Chen, Hsinchu County, TW;

Cheng-I Huang, Hsinchu, TW;

Jung-Chan Yang, Taoyuan, TW;

Hsiang-Jen Tseng, Hsinchu, TW;

Chi-Yu Lu, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H03K 17/693 (2013.01);
Abstract

A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.


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