The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Oct. 26, 2017
Applicant:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Zhongshan Hong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/461 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01L 29/66 (2006.01); H01L 29/772 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/0802 (2013.01); H01L 28/24 (2013.01);
Abstract

An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.


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