The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Dec. 11, 2014
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Gerald Suiter, Madison, AL (US);

Edwin Smith, Athens, AL (US);

Henry Potts, Ft. Collins, CO (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 3/0484 (2013.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); G06F 3/023 (2006.01); G06F 1/16 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G06F 1/1652 (2013.01); G06F 3/023 (2013.01); G06F 3/04842 (2013.01); G06F 17/5045 (2013.01); G06F 17/5068 (2013.01); G06F 2203/0338 (2013.01); G06F 2217/40 (2013.01); H05K 1/0298 (2013.01); H05K 3/46 (2013.01);
Abstract

This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.


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