The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Feb. 15, 2016
Supporting flow control mechanism of bus between semiconductor dies assembled in wafer-level package
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventor:
Yao-Chun Su, Hsinchu, TW;
Assignee:
Nephos (Hefei) Co. Ltd., Hefei, Anhui, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); H01L 23/498 (2006.01); G06F 13/368 (2006.01); G06F 13/40 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 13/368 (2013.01); G06F 13/4068 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 25/065 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06527 (2013.01);
Abstract
A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.