The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

May. 15, 2017
Applicant:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Inventors:

Chih-Hong Chuang, Hsinchu County, TW;

Chien-Hung Wu, Hsinchu County, TW;

Assignee:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H01K 1/00 (2006.01); H05K 1/09 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/18 (2006.01); H05K 3/40 (2006.01); H05K 3/20 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/09 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/49822 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 3/18 (2013.01); H05K 3/205 (2013.01); H05K 3/4038 (2013.01); H05K 3/4638 (2013.01); H05K 3/4644 (2013.01); H05K 3/4682 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68381 (2013.01); H05K 3/007 (2013.01); H05K 3/0026 (2013.01); H05K 3/0047 (2013.01); H05K 3/421 (2013.01); H05K 2201/09509 (2013.01); H05K 2203/03 (2013.01);
Abstract

A temporary package substrate includes a first copper layer, a second copper layer, a third copper layer, a first plating copper layer, a second plating copper layer, a third plating copper layer, a first dielectric layer, a second dielectric layer and two circuit structures. The second copper layer is located between the first and the third copper layers, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer. The first and the second dielectric layers completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer. Each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.


Find Patent Forward Citations

Chuang, Chih-Hong. (2018). Package substrate and manufacturing method thereof (U.S. Patent No. 10123413). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10123413

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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