The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Jun. 20, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ahmed Fouad Salama, Chandler, AZ (US);
Srikrishnan Venkataraman, Bangalore, IN;
Todd W. Mellinger, Fort Collins, CO (US);
Michael J. Hill, Gilbert, AZ (US);
Paul K. Tucker, Chandler, AZ (US);
Assaf Benhamou, Haifa, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01); G05F 1/565 (2006.01); H02J 13/00 (2006.01); H02J 3/06 (2006.01); B06B 1/02 (2006.01); H02J 5/00 (2016.01); H02J 50/80 (2016.01); H04J 14/02 (2006.01);
U.S. Cl.
CPC ...
H02J 13/0075 (2013.01); B06B 1/0207 (2013.01); H02J 3/06 (2013.01); H02J 5/005 (2013.01); H02J 50/80 (2016.02); H04J 14/02 (2013.01);
Abstract
An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.