The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Aug. 31, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Tomohiro Uno, Yokkaichi, JP;

Shiori Kataoka, Yokkaichi, JP;

Yusuke Yoshida, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); G11C 11/56 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/06 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); H01L 27/24 (2013.01); H01L 45/124 (2013.01); H01L 45/145 (2013.01); H01L 45/149 (2013.01); H01L 45/1608 (2013.01); H01L 45/1666 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01);
Abstract

An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conformal barrier material layer in the laterally recessed regions and on the sidewalls of the insulating layers, an amorphous precursor memory material layer is deposited in lateral cavities and over the conformal barrier material layer. An anneal process is performed to selectively crystallize portions of the amorphous precursor memory material layer in the lateral cavities into crystalline memory material portions while not crystallizing portions of the amorphous precursor memory material outside the lateral cavities. Remaining amorphous portions of the amorphous precursor memory material layer are removed selective to the crystalline memory material portions. A vertical conductive line is formed on the crystalline memory material portions. The crystalline memory material portions are formed as discrete self-aligned material portions.


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