The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Jun. 16, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Yinjie Ding, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Kangho Lee, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); G11C 11/1675 (2013.01); H01L 27/228 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01);
Abstract

A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.


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