The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Dec. 05, 2017
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Weichang Liu, Singapore, SG;

Zhen Chen, Singapore, SG;

Shen-De Wang, Zhudong Township, TW;

Wang Xiang, Singapore, SG;

Wei Ta, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/06 (2006.01); H01L 27/11568 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 27/11568 (2013.01); H01L 29/0653 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.


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