The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Nov. 16, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Tieh-Chiang Wu, Taoyuan, TW;

Shing-Yih Shih, New Taipei, TW;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/304 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 29/92 (2006.01); C23C 14/16 (2006.01); C23C 16/06 (2006.01); C23C 16/40 (2006.01); C23C 16/34 (2006.01); C23C 14/06 (2006.01); C23C 14/10 (2006.01); C23C 14/08 (2006.01); H01L 21/3065 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); C23C 14/0652 (2013.01); C23C 14/08 (2013.01); C23C 14/10 (2013.01); C23C 14/16 (2013.01); C23C 16/06 (2013.01); C23C 16/345 (2013.01); C23C 16/402 (2013.01); H01L 21/304 (2013.01); H01L 21/3065 (2013.01); H01L 21/30625 (2013.01); H01L 21/7684 (2013.01); H01L 21/76841 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 29/66181 (2013.01); H01L 29/92 (2013.01); H01L 21/76865 (2013.01); H01L 21/76883 (2013.01); H01L 28/90 (2013.01);
Abstract

A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.


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