The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Sep. 19, 2016
Toshiba Memory Corporation, Minato-ku, JP;
Shigeki Kobayashi, Kuwana, JP;
Satoshi Konagai, Kasugai, JP;
Atsushi Konno, Yokkaichi, JP;
Kenta Yamada, Yokkaichi, JP;
Masaaki Higuchi, Yokkaichi, JP;
Masao Shingu, Yokkaichi, JP;
Soichiro Kitazaki, Yokohama, JP;
Yoshimasa Mikajiri, Mie, JP;
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Abstract
According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.