The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Sep. 14, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Takeshi Sonehara, Yokkaichi, JP;

Masaru Kito, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11575 (2013.01);
Abstract

According to embodiments, a semiconductor memory device includes a plurality of control gate electrodes laminated on a substrate. A first semiconductor layer has one end connected to the substrate, has a longitudinal direction in a direction intersecting with the substrate, and is opposed to the plurality of control gate electrodes. An electric charge accumulating layer is positioned between this control gate electrode and the first semiconductor layer. A first contact has one end connected to the substrate and another end connected to a source line. A second contact has one end connected to the substrate and another end connected to a wiring other than the source line. The first contact includes a first silicide layer arranged on the substrate. The second contact includes a second silicide layer arranged on the substrate. The first silicide layer has a higher temperature resistance than the second silicide layer.


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