The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Mar. 20, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Robert H. Dennard, Cronton-on-Hudson, NY (US);

Isaac Lauer, Yorktown Heights, NY (US);

Ramachandran Muralidhar, Mahopac, NY (US);

Ghavam G. Shahidi, Pound Ridge, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/308 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/0257 (2013.01); H01L 21/02181 (2013.01); H01L 21/02192 (2013.01); H01L 21/02532 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/3081 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66818 (2013.01);
Abstract

In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.


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