The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Jan. 22, 2018
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Kuo-Ting Lin, Hsinchu County, TW;

Chia-Wei Chang, Hsinchu County, TW;

Assignee:

Powertech Technology Inc., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 21/486 (2013.01); H01L 21/568 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 25/0657 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13027 (2013.01); H01L 2224/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1816 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.


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