The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Jun. 12, 2017
Intel Corporation, Santa Clara, CA (US);
Ned M. Smith, Beaverton, OR (US);
Rajesh Poornachandran, Portland, OR (US);
Abdul M. Bailey, Tigard, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.