The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Dec. 12, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shiliang Hu, Los Altos, CA (US);

Gilles A. Pokam, Fremont, CA (US);

Cristiano L. Pereira, Groveland, CA (US);

Justin E. Gottschlich, Santa Clara, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 9/45 (2006.01); G06F 11/36 (2006.01); G06F 9/52 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3632 (2013.01); G06F 9/526 (2013.01); G06F 11/30 (2013.01); G06F 11/3409 (2013.01); G06F 11/3419 (2013.01); G06F 11/3466 (2013.01);
Abstract

Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.


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