The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Jul. 05, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Stefan Singer, Vaterstetten, DE;
Jochen M Gerster, Stuttgart, DE;
Michael Rohleder, Unterschleissheim, DE;
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/38 (2018.01); G06F 12/0862 (2016.01); G06F 12/08 (2016.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/38 (2013.01); G06F 9/3802 (2013.01); G06F 9/3814 (2013.01); G06F 9/3842 (2013.01); G06F 9/46 (2013.01); G06F 9/48 (2013.01); G06F 9/4806 (2013.01); G06F 9/4843 (2013.01); G06F 12/08 (2013.01); G06F 12/0862 (2013.01); G06F 9/461 (2013.01);
Abstract
Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.