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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10120684 B1

PDFFull Text
Date of Patent:
Nov. 06, 2018

Filed:

Mar. 11, 2013

Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Doron Orenstien, Hiafa, IL;

Zeev Sperber, Zichron Yackov, IL;

Robert Valentine, Kiryat Tivon, IL;

Benny Eitan, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

NDWE, LLP

Primary Examiner:

David J Huisman

Int. Cl.
CPC ...
G06F 9/312 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/30018 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30072 (2013.01); G06F 9/30145 (2013.01); G06F 9/3842 (2013.01); G06F 9/3861 (2013.01); G06F 15/8061 (2013.01);
Abstract

Logic is provided to receive and execute a mask move instruction to transfer unmasked data elements of a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. The logic is to execute a speculative full width operation, and if an exception occurs is to perform operations sequentially or one at a time. Other embodiments are described and claimed.

Find Patent Forward Citations

Quick Actions:

Orenstien, Doron. (2018). Instructions and logic to perform mask load and store operations as sequential or one-at-a-time operations after exceptions and for un-cacheable type memory (U.S. Patent No. 10120684). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10120684

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