Vertical field effect transisitors having a rectangular surround gate and method of making the same

Abstract

Dielectric wall structures are formed through a stack of a doped semiconductor material layer, a planar insulating spacer layer, and a sacrificial matrix layer. Gate electrode rails are formed through the dielectric wall structures and the sacrificial matrix layer. A two-dimensional array of rectangular openings is formed by removing remaining portions of the sacrificial matrix layer. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of rectangular openings. Gate dielectrics are formed on sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surround gates is formed, which may be employed as access transistors of a three-dimensional memory device.