The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Apr. 07, 2017
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chun-Hsiao Li, Zhubei, TW;

Wei-Ren Chen, Pingtung, TW;

Hsueh-Wei Chen, Hsinchu, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); G11C 16/14 (2006.01); H01L 27/11507 (2017.01); H01L 27/11529 (2017.01); H01L 29/423 (2006.01); G06F 7/58 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 16/04 (2006.01); H01L 27/11558 (2017.01); H01L 49/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); G06F 7/588 (2013.01); G11C 16/0441 (2013.01); G11C 16/14 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/5226 (2013.01); H01L 27/0883 (2013.01); H01L 27/11507 (2013.01); H01L 27/11529 (2013.01); H01L 27/11558 (2013.01); H01L 28/00 (2013.01); H01L 29/0653 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/7841 (2013.01); G11C 2216/10 (2013.01); H01L 29/7831 (2013.01); H01L 29/7833 (2013.01);
Abstract

An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.


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