Address decoder for a non-volatile memory array using mos selection transistors

Abstract

An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (V) and column-driving signals (V), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (V) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.