The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Apr. 19, 2016
Applicant:
Spin Transfer Technologies, Inc., Fremont, CA (US);
Inventors:
Benjamin Stanley Louie, Fremont, CA (US);
Neal Berger, Cupertino, CA (US);
Assignee:
SPIN TRANSFER TECHNOLOGIES, INC., Fremont, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 11/16 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G06F 3/0619 (2013.01); G06F 3/0653 (2013.01); G06F 3/0688 (2013.01); G06F 11/076 (2013.01); G06F 11/0727 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01);
Abstract
A nonvolatile error buffer is added to STT-MRAM memory design to reduce the error correction coding ECC required to achieve reliable operation with a non-zero Write Error Rate ('WER'). The error buffer is fully associative, storing both the address and the data of memory words which have failed to write correctly within an assigned ECC error budget. The write cycle includes a verify to determine if the word has been written correctly. The read cycle includes a search of the error buffer to determine if the address is present in the buffer.