The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2018
Filed:
Sep. 28, 2016
Applicants:
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Inventors:
Kei Fukui, Iizuna, JP;
Kazuya Arai, Suzaka, JP;
Koji Komemura, Nagano, JP;
Kazuhiko Iijima, Kawasaki, JP;
Kenichiro Abe, Nagano, JP;
Shinji Rokuhara, Minato, JP;
Shuichi Oka, Minato, JP;
Assignees:
FUJITSU LIMITED, Kawasaki, JP;
SONY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/18 (2006.01); H05K 7/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H05K 1/02 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/02 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01); H05K 1/14 (2006.01); H05K 3/42 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 1/144 (2013.01); H05K 3/002 (2013.01); H05K 3/0026 (2013.01); H05K 3/02 (2013.01); H05K 3/4038 (2013.01); H05K 3/429 (2013.01); H05K 3/4652 (2013.01); H05K 3/4682 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H05K 1/162 (2013.01); H05K 2201/041 (2013.01); H05K 2201/096 (2013.01); H05K 2201/10371 (2013.01); H05K 2203/0156 (2013.01);
Abstract
A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.