The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Jun. 05, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yoshisato Yokoyama, Tokyo, JP;

Yoshikazu Saito, Tokyo, JP;

Shunya Nagata, Tokyo, JP;

Toshiaki Sano, Tokyo, JP;

Takeshi Hashizume, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/405 (2006.01); G11C 7/06 (2006.01); G11C 8/16 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); H03K 19/177 (2006.01); G11C 29/02 (2006.01); G11C 29/32 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/405 (2013.01); G11C 7/062 (2013.01); G11C 8/16 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01); G11C 11/40603 (2013.01); G11C 29/024 (2013.01); G11C 29/32 (2013.01); H03K 19/1776 (2013.01); G11C 2029/1202 (2013.01); G11C 2207/104 (2013.01);
Abstract

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.


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