The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Apr. 24, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Jeffrey W. Scott, Austin, TX (US);

William C. Moyer, Dripping Springs, TX (US);

Quyen Pho, Pflugerville, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 9/52 (2006.01); G06F 12/0875 (2016.01); G06F 12/0862 (2016.01); G06F 9/38 (2018.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/528 (2013.01); G06F 9/3802 (2013.01); G06F 9/3804 (2013.01); G06F 9/3861 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6028 (2013.01);
Abstract

A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.


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