The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Mar. 21, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vjekoslav Svilan, Sunnyvale, CA (US);

David N. Mackintosh, Mountain View, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 1/32 (2006.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4893 (2013.01); G06F 1/329 (2013.01); G06F 1/3243 (2013.01); G06F 8/4432 (2013.01); Y02D 10/152 (2018.01); Y02D 10/24 (2018.01);
Abstract

In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.


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