The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Aug. 16, 2017
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventor:

Richard Stephen Roy, Dublin, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); G01R 31/28 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2831 (2013.01); H01L 21/823412 (2013.01); H01L 27/092 (2013.01); H01L 29/152 (2013.01); H01L 29/7843 (2013.01); H01L 29/7849 (2013.01);
Abstract

A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.


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