Low jitter pulse output for power meter

Abstract

There is provided an energy consumption meter device comprising including a processor arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ΔE using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n−1]. The processor will then calculate a relative delay Td' using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td′ with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.